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Figure 6-53 shows a DMA startup sequence from the backend interface. Initially, the backend requests access to the bus
by asserting BE_REQ. When granted, it writes to the four DMA registers (cycles B2–B5), writing to the control
register last. Three clock cycles after the write to the control register, the core asserts the PCI bus request and carries out
a normal DMA transfer.
cycle
B0 B1 B2 B3 B4 B5 B6
A0 A1 A2 A3 0
1
2
3
4
5
6
7
8
clk
framen
cben[3:0]
7
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
reqn
gntn
be_req
be_gnt
be_address[7:0]
be_write
mast_active
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
mem_add[11:0]
50 54 58 5C
0
004 008 00C 010 014
mem_data_in[31:0]
PA RA TC CR
0
1
2
3
4
5
rd_sync
Figure 6-53 · DMA Register Access and DMA Startup
100
v4.0
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